1. Field
Exemplary embodiments of the present invention relate generally to a semiconductor design technology and, more particularly, to a stacked memory device capable of performing a wafer-level test and a semiconductor memory system including the same.
2. Description of the Related Art
As the semiconductor memory technology has developed rapidly, there is a growing need for a high degree of integration and high performance for a packaging technology for semiconductor integration devices. A two-dimensional (2D) structure, in which semiconductor chips having integration circuits are disposed on a printed circuit board (PCB) using wires or bumps, have been used in the past as conventional packaging technology. More recently, various three-dimensional (3D) structure technologies employing a plurality of semiconductor chips stacked on top of one another are being developed.
More specifically, a plurality of memory chips are typically vertically stacked in a stacked memory device having a 3D structure. Furthermore, the semiconductor chips which are stacked in a vertical direction are electrically coupled through one or more through-chip electrodes, for example, through-silicon vias (TSVs) and are mounted on a substrate for a semiconductor package.
Due to the increased complexity of a stacked memory device new methods are being developed for ensuring product quality requiring testing both at the wafer level as well as after assembly of the wafers into the packaged stacked structure has been completed. Hence, typically a method for testing a stacked memory device employing TSVs may include a package-level test method for testing the stacked memory device after it has been assembled into a packaged product and a wafer-level test method performed in a wafer state prior to the assembling process.